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1/14 february 2001 M27C322 32 mbit (2mb x16) uv eprom and otp eprom n 5v 10% supply voltage in read operation n access time: 80ns n word-wide configurable n 32 mbit mask rom replacement n low power consumption C active current 50ma at 5mhz C stand-by current 100a n programming voltage: 12v 0.25v n programming time: 50s/word n electronic signature C manufacturer code: 0020h C device code: 0034h description the M27C322 is a 32 mbit eprom offered in the uv range (ultra violet erase). it is ideally suited for microprocessor systems requiring large data or program storage. it is organised as 2 mwords of 16 bit. the pin-out is compatible with a 32 mbit mask rom. the fdip42w (window ceramic frit-seal package) has a transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. a new pattern can then be written rapidly to the device by following the programming proce- dure. for applications where the content is programmed only one time and erasure is not required, the M27C322 is offered in pdip42 and sdip42 pack- ages. 1 42 1 42 fdip42w (f) pdip42 (b) 1 42 sdip42 (s) figure 1. logic diagram ai02156 21 a0-a20 gv pp q0-q15 v cc M27C322 e v ss 16
M27C322 2/14 figure 2. dip connections gv pp q0 q8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 q7 a12 a16 a20 q15 q5 q2 q3 v cc q11 q4 q14 a9 a8 a17 a4 a18 a19 a7 ai02157 M27C322 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 q1 q9 a6 a5 q6 q13 42 39 38 37 36 35 34 33 a11 a10 q10 21 q12 40 41 from e to output (t elqv ). data is available at the output after a delay of t glqv from the falling edge of g v pp , assuming that e has been low and the addresses have been stable for at least t avqv - t glqv . standby mode the M27C322 has a standby mode which reduces the supply current from 50ma to 100a. the M27C322 is placed in the standby mode by apply- ing a cmos high signal to the e input.when in the standby mode, the outputs are in a high imped- ance state, independent of the g v pp input. two line output control because eproms are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. the two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficient use of these two control lines, e should be decoded and used as the prima- ry device selecting function, while g v pp should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. table 1. signal names a0-a20 address inputs q0-q15 data outputs e chip enable g v pp output enable / program supply v cc supply voltage v ss ground device operation the operating modes of the M27C322 are listed in the operating modes table. a single power supply is required in the read mode. all inputs are ttl compatible except for v pp and 12v on a9 for the electronic signature. read mode the M27C322 has a word-wide organization. chip enable (e ) is the power control and should be used for device selection. output enable (g ) is the output control and should be used to gate data to the output pins independent of device selection. assuming that the addresses are stable, the ad- dress access time (t avqv ) is equal to the delay
3/14 M27C322 table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum dc voltage on input or output is C0.5v with possible undershoot to C2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5v with possible overshoot to v cc +2v for a period less than 20ns. 3. depends on range. table 3. operating modes note: x = v ih or v il , v id = 12v 0.5v. table 4. electronic signature note: outputs q15-q8 are set to '0'. symbol parameter value unit t a ambient operating temperature (3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage (except a9) C2 to 7 v v cc supply voltage C2 to 7 v v a9 (2) a9 voltage C2 to 13.5 v v pp program supply voltage C2 to 14 v mode e g v pp a9 q15-q0 read v il v il x data out output disable v il v ih x hi-z program v il pulse v pp x data in program inhibit v ih v pp x hi-z standby v ih x x hi-z electronic signature v il v il v id codes identifier a0 q7 q6 q5 q4 q3 q2 q1 q0 hex data manufacturers code v il 00100000 20h device code v ih 00110100 34h
M27C322 4/14 table 5. ac measurement conditions high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v figure 3. ac testing input output waveform ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 4. ac testing load circuit ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test table 6. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 10 pf c out output capacitance v out = 0v 12 pf put control and by properly selected decoupling capacitors. it is recommended that a 0.1f ceram- ic capacitor is used on every device between v cc and v ss . this should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. in addition, a 4.7f electrolytic capacitor should be used be- tween v cc and v ss for every eight devices. this capacitor should be mounted near the power sup- ply connection point. the purpose of this capacitor is to overcome the voltage drop caused by the in- ductive effects of pcb traces. system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the supplies to the devices. the supply current icc has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of e . the magnitude of the transient current peaks is dependent on the ca- pacitive and inductive loading of the device out- puts. the associated transient voltage peaks can be suppressed by complying with the two line out-
5/14 M27C322 table 7. read mode dc characteristics (1) (t a = 0 to 70 c, C40 to 85 c or C40 to 125 c; v cc = 5v 10%; v pp = v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v. table 8. read mode ac characteristics (1) (t a = 0 to 70 c, C40 to 85 c or C40 to 125 c; v cc = 5v 10%; v pp = v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp 2. sampled only, not 100% tested. 3. speed obtained with high speed ac measurement conditions. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 10 a i cc supply current e = v il , g v pp = v il , i out = 0ma, f = 8mhz 70 ma e = v il , g v pp = v il , i out = 0ma, f = 5mhz 50 ma i cc 1 supply current (standby) ttl e = v ih 1ma i cc 2 supply current (standby) cmos e > v cc C 0.2v 100 a i pp program current v pp = v cc 10 a v il input low voltage C0.3 0.8 v v ih (2) input high voltage 2 v cc + 1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C400a 2.4 v symbol alt parameter test condition M27C322 unit -80 (3) -100 min max min max t avqv t acc address valid to output valid e = v il , g v pp = v il 80 100 ns t elqv t ce chip enable low to output valid g v pp = v il 80 100 ns t glqv t oe output enable low to output valid e = v il 40 50 ns t ehqz (2) t df chip enable high to output hi-z g v pp = v il 0 40 0 40 ns t ghqz (2) t df output enable high to output hi-z e = v il 0 40 0 40 ns t axqx t oh address transition to output transition e = v il , g v pp = v il 55ns
M27C322 6/14 figure 5. read mode ac waveforms ai02207 taxqx tehqz a0-a20 e gv pp q0-q15 tavqv tghqz tglqv telqv valid hi-z valid table 9. programming mode dc characteristics (1) (t a = 25 c; v cc = 6.25v 0.25v; v pp = 12v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . symbol parameter test condition min max unit i li input leakage current v il v in v ih 10 m a i cc supply current 50 ma i pp program current e = v il 50 ma v il input low voltage C0.3 0.8 v v ih input high voltage 2.4 v cc + 0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C2.5ma 3.5 v v id a9 voltage 11.5 12.5 v
7/14 M27C322 table 10. margin mode ac characteristics (1) (t a = 25 c; v cc = 6.25v 0.25v; v pp = 12v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . table 11. programming mode ac characteristics (1) (t a = 25 c; v cc = 6.25v 0.25v; v pp = 12v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol alt parameter test condition min max unit t a9hvph t as9 v a9 high to v pp high 2 s t vphel t vps v pp high to chip enable low 2s t a10heh t as10 v a10 high to chip enable high (set) 1s t a10leh t as10 v a10 low to chip enable high (reset) 1s t exa10x t ah10 chip enable transition to v a10 transition 1s t exvpx t vph chip enable transition to v pp transition 2s t vpxa9x t ah9 v pp transition to v a9 transition 2s symbol alt parameter test condition min max unit t av el t as address valid to chip enable low 1 s t qvel t ds input valid to chip enable low 1 s t vchel t vcs v cc high to chip enable low 2s t vphel t oes v pp high to chip enable low 1s t vplvph t prt v pp rise time 50 ns t eleh t pw chip enable program pulse width (initial) 45 55 s t ehqx t dh chip enable high to input transition 2 s t ehvpx t oeh chip enable high to v pp transition 2s t vplel t vr v pp low to chip enable low 1s t elqv t dv chip enable low to output valid 1 s t ehqz (2) t dfp chip enable high to output hi-z 0 130 ns t ehax t ah chip enable high to address transition 0 ns programming when delivered (and after each erasure for uv eprom), all bits of the M27C322 are in the "1" state. data is introduced by selectively program- ming "0"s into the desired bit locations. although only "0"s will be programmed, both "1"s and "0"s can be present in the data word. the only way to change a "0" to a "1" is by die exposition to ultravi- olet light (uv eprom). the M27C322 is in the programming mode when v pp input is at 12.v, g v pp is at v ih and e is pulsed to v il . the data to be programmed is applied to 16 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. v cc is specified to be 6.25v 0.25v.
M27C322 8/14 figure 6. margin mode ac waveforms note: a8 high level = 5v; a9 high level = 12v. figure 7. programming and verify modes ac waveforms note: g v pp high level = 12v. ai00736b ta9hvph tvpxa9x a8 e gv pp a10 set v cc tvphel ta10leh texvpx ta10heh a9 a10 reset texa10x tavel valid ai02205 a0-a20 q0-q15 v cc data in data out e tqvel tvchel tvphel tehqx tehvpx telqv teleh tehqz tvplel program verify gv pp tehax
9/14 M27C322 presto iii programming algorithm the presto iii programming algorithm allows the whole array to be programed with a guaran- teed margin in a typical time of 100 seconds. pro- gramming with presto iii consists of applying a sequence of 50 s program pulses to each word until a correct verify occurs (see figure 8). during programing and verify operation a margin mode circuit must be activated to guarantee that each cell is programed with enough margin. no overprogram pulse is applied since the verify in margin mode provides the necessary margin to each programmed cell. program inhibit programming of multiple M27C322s in parallel with different data is also easily accomplished. ex- cept for e , all like inputs including g v pp of the par- allel M27C322 may be common. a ttl low level pulse applied to a M27C322's e input and v pp at 12v, will program that M27C322. a high level e in- put inhibits the other M27C322s from being pro- grammed. figure 8. programming flowchart ai02206 n = 0 last addr verify e = 50 m s pulse ++n = 25 ++ addr v cc = 6.25v, v pp = 12v fail check all words 1st: v cc = 6v 2nd: v cc = 4.2v yes no yes no yes no set margin mode reset margin mode program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. the verify is accomplished with g v pp at v il . data should be verified with t elqv af- ter the falling edge of e . electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the es mode is functional in the 25c 5c am- bient temperature range that is required when pro- gramming the M27C322. to activate the es mode, the programming equipment must force 11.5v to 12.5v on address line a9 of the M27C322, with v pp = v cc = 5v. two identifier bytes may then be sequenced from the device out- puts by toggling address line a0 from v il to v ih . all other address lines must be held at v il during electronic signature mode. byte 0 (a0 = v il ) represents the manufacturer code and byte 1 (a0 = v ih ) the device identifier code. for the stmicroelectronics M27C322, these two identifier bytes are given in table 4 and can be read-out on outputs q0 to q7. erasure operation (applies to uv eprom) the erasure characteristics of the M27C322 is such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 ?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 ? range. research shows that constant exposure to room level fluo- rescent lighting could erase a typical M27C322 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the M27C322 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C322 window to prevent unintentional era- sure. the recommended erasure procedure for M27C322 is exposure to short wave ultraviolet light which has a wavelength of 2537 ?. the inte- grated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 30 w-sec/cm 2 . the erasure time with this dosage is approximate- ly 30 to 40 minutes using an ultraviolet lamp with 12000 w/cm 2 power rating. the M27C322 should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be removed before erasure.
M27C322 10/14 table 12. ordering information scheme note: 1. high speed, see ac characteristics section for further information. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: M27C322 -80 f 1 device type m27 supply voltage c = 5v 10% device function 322 = 32 mbit (2mb x16) speed -80 (1) = 80 ns -100 = 100 ns package f = fdip42w b = pdip42 s = sdip42 temperature range 1 = 0 to 70 c 3 = C40 to 125 c 6 = C40 to 85 c table 13. revision history date revision details july 1999 first issue 02/24/00 programming time changed programming flowchart changed (figure 8) presto iii programming algorithm paragraph changed 04/04/00 C40 to 85 c and C40 to 125 c temperature ranges added (table 7, 8 and 12) 80ns speed class in high speed ac measurement conditions 09/20/00 an620 reference removed 11/29/00 note changed (figure 7) 02/27/01 sdip42 package added (figure 11, table 16)
11/14 M27C322 table 14. fdip42w - 42 pin ceramic frit-seal dip with window, package mechanical data symbol millimeters inches typ min max typ min max a 5.72 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 0.177 b 0.41 0.56 0.016 0.022 b1 1.45 C C 0.057 C C c 0.23 0.30 0.009 0.012 d 54.41 54.86 2.142 2.160 d2 50.80 C C 2.000 C C e 15.24 C C 0.600 C C e1 14.50 14.90 0.571 0.587 e 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 16.18 18.03 0.637 0.710 l 3.18 4.10 0.125 0.161 s 1.52 2.49 0.060 0.098 k 8.00 C C 0.315 C C k1 16.00 C C 0.630 C C a 4 11 4 11 n42 42 figure 9. fdip42w - 42 pin ceramic frit-seal dip with window, package outline note: drawing is not to scale. fdipw-b a3 a1 a l b1 b e1 d s e1 e n 1 c ea d2 k k1 a eb a2
M27C322 12/14 table 15. pdip42 - 42 pin plastic dip, 600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a C 5.08 C 0.200 a1 0.25 C 0.010 C a2 3.56 4.06 0.140 0.160 b 0.38 0.53 0.015 0.021 b1 1.27 1.65 0.050 0.065 c 0.20 0.36 0.008 0.014 d 52.20 52.71 2.055 2.075 d2 50.80 C C 2.000 C C e 15.24 C C 0.600 C C e1 13.59 13.84 0.535 0.545 e1 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 0.86 1.37 0.034 0.054 a 0 10 0 10 n42 42 figure 10. pdip42 - 42 pin plastic dip, 600 mils width, package outline note: drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
13/14 M27C322 table 16. sdip42 - 42 pin shrink plastic dip, 600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a 5.08 0.200 a1 0.51 0.020 a2 3.81 3.05 4.57 0.150 0.120 0.180 b 0.46 0.38 0.56 0.018 0.015 0.022 b2 1.02 0.89 1.14 0.040 0.035 0.045 c 0.25 0.23 0.38 0.010 0.009 0.015 d 36.83 36.58 37.08 1.450 1.440 1.460 e 1.78 C C 0.070 C C e 15.24 16.00 0.600 0.630 e1 13.72 12.70 14.48 0.540 0.500 0.570 ea 15.24 C C 0.600 C C eb 18.54 0.730 l 3.30 2.54 3.56 0.130 0.100 0.140 s 0.64 0.025 n42 42 figure 11. sdip42 - 42 pin shrink plastic dip, 600 mils width, package outline note: drawing is not to scale. sdip a2 a1 a l b2 b e d s e1 e n 1 c ea eb d2
M27C322 14/14 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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